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73S8009CN combo iso - 7816 and usb universal smart card interface ic simplifying system integration ? data sheet ds_8009c_026 august 2009 rev. 1.4 ? 2009 terid ian semiconductor corporation 1 description the teridian 73S8009CN is the world?s first single - chip smart card electrical interface circuit that supports all types of smart cards: 5v, 3v and 1.8v, including traditional iso - 7816 - 3 asynchronous and synchronous type 1 and type 2, as well as usb, iso - 7816 - 12 cards. the 73S8009CN is ideally suited for applications such as desktop computers, laptops and general purpose smart card readers that require low power operation from a single 2.7v to 6.5v power supply voltage source. a power d own mode (?off? mode) is available and exhibits a 10na typical current consumption. the circuit provides control, conversion and regulation of power for the smart card. in addition, the circuit provides a 3.3v - regulated voltage that is used as an internal digital supply voltage to the host interface. it is also made available to supply power to some external circuitry (a host controller for instance). for asynchronous and synchronous smart card operation, the signals for rst, clk, i/o and auxiliary signal s aux1 and aux2 are directly controlled from the host processor and are level - shifted by the circuit to the selected v cc value . for more design flexibility, the host processor is responsible for handling the signal timing for smart card activation and de - activation under normal conditions. the power management circuitry allows operation from a single power supply source v pc (2.7v to 6.5v). v pc is converted using an inductive, step - up power converter to the intermediate voltage, v p . v p is used by linear v oltage regulators and switches internal to the ic to create the voltages v dd and as required, v cc . v dd is used by the 73S8009CN and is also made available for the companion host processor circuit or for other external circuits. the 73S8009CN features an o n/off pin suitable to connect to a ?push - on/push - off? main system switch. when the 73S8009CN is ?off,? the typical current drawn from vpc is 10na. for applications that do not implement any on/off system switch, the on/off input pin can be driven from a digital output of the host processor. features ? smart card interface: ? smart card voltage v cc : o selectable: 1.8v, 3v or 5v o generated by an internal voltage regulator o provides up to 65ma to 3v and 5v cards and up to 40ma to 1.8v cards ? iso - 7816 - 3 card emerge ncy deactivation ? voltage supervisor detects voltage drop on v cc (card supply) ? true card over - current detection 150ma max. ? 1 input for a card presence detection switch ? auxiliary i/o lines for synchronous and iso - 7816 - 12 usb card support ? proper isolation o f smart card signals depending on smart card type ? card clk clock frequency up to 20mhz ? 6kv esd and short circuit protection on the card interface ? system controller interface: ? digital logic level: 3.3v ? 5 signal images of the card signals (rstin, clkin, i/o uc, aux1uc and aux2uc) ? 1 control signal to switch between synchronous / asynchronous and iso - 7816 - 12 usb smart card modes ? 2 inputs activate and select the card voltage ( cmdvcc% and cmdvcc# ) ? 2 outputs, interrupt to the system controller ( off and rdy), to i nform the system controller of the card presence / faults and status of the interface ? 1 chip select input ? 2 handshaking signals (off_req, off_ack) for proper shutdown sequencing of all smart card signals ? on/off input for a main system switch ? dc- dc step - u p converter: ? generates an intermediary voltage v p ? requires a single 10 h inductor (rated for 400ma maximum peak current) ? v dd power supply output available to power up external circuitry: 3.3v 0.3v, 40ma ? industrial temperature range ( - 40 c to +85 c) ? small format qfn32 package: 5x5mm ? rohs compliant (6/6) lead - free package
73S8009CN data sheet ds_8009cn_026 2 rev. 1.4 functional diagram v pc v dd dp v cc l in rdy cmdv cc# cmdv cc% delay/ debounce circuit 3.3v regulator cs v cc regulator linear/ dc - dc converter v1.8 th ref v3.0 th ref v5.0 th ref analog mux v p on off v p shutdown dm + - 10 f 0.47 f 4.7 f 10uh i/o rst clk aux1 aux2 i/ouc rstin clkin aux1uc aux2uc pres sc/ usb gnd gnd gnd off card i/o buffer and signal logic 0.1 f 0.1 f on/off off_req off_ack debounce and latch 100k card supply and control logic 0.1 f vcc status test1 test2 to internal digital logic 24k figure 1 : 73S8009CN block diagram
ds_8009cn_026 73S8009CN data sheet rev. 1.4 3 table of contents 1 pinout ............................................................................................................................................. 5 2 electrical specifications ................................................................................................................ 9 2.1 absolute maximum ratings ..................................................................................................... 9 2.2 recommended operating conditions ...................................................................................... 9 2.3 smart card interface requirements ...................................................................................... 10 2.4 digital signals characteristics ............................................................................................... 12 2.5 dc cha racteristics ................................................................................................................ 13 2.6 voltage / temperature fault detection circuits ...................................................................... 13 2.7 thermal characteristics ........................................................................................................ 13 3 applications information ............................................................................................................. 13 3.1 example 73S8009CN schematics ......................................................................................... 13 3.2 power supply and conv erter ................................................................................................. 16 3.3 interface function - on/off modes ...................................................................................... 16 3.4 system controller interface ................................................................................................... 18 3.5 card power supply and voltage supervision ......................................................................... 18 3.6 activation and de - activation sequence ................................................................................. 19 3.7 off and f ault detection ....................................................................................................... 20 3.8 chip selection ....................................................................................................................... 21 3.9 i/o circuitry and timing ......................................................................................................... 22 4 equivalent circuits ...................................................................................................................... 24 5 mechanical drawing .................................................................................................................... 28 6 ordering information ................................................................................................................... 29 7 related documentation ............................................................................................................... 29 8 contact information ..................................................................................................................... 29
73S8009CN data sheet ds_8009cn_026 4 rev. 1.4 figures figure 1: 73S8009CN b lock diagram ...................................................................................................... 2 figure 2: 73S8009CN 32 - pin qfn pinout ................................................................................................ 5 figure 3: typical 73S8009CN application schematic with a main system swit ch ................................... 14 figure 4: typical 73S8009CN application schematic without a main system switch .............................. 15 figure 5: activation sequence ............................................................................................................... 19 figure 6: deactivation sequence ........................................................................................................... 20 figure 7: off activity ............................................................................................................................ 20 figure 8: cs timing definitions .............................................................................................................. 21 figure 9: i/o and i/ouc state diagram .................................................................................................. 22 figure 10: i/o ? i/ouc delays - timing diagram .................................................................................... 23 figure 11: on_off pin ............................................................................................................................ 24 figure 12: open drain type ? off and rdy .......................................................................................... 24 figure 13: power input/output circuit, vdd, lin, vpc, vcc, vp ........................................................... 24 figure 14: usb ? dm, dp pins .............................................................................................................. 25 figure 15: smart card clk driver circu it .............................................................................................. 25 figure 16: smart card rst driver circuit .............................................................................................. 25 figure 17: smart card io, aux1, and aux2 interface circuit ................................................................. 26 figure 18: smart card iouc, aux1uc and aux2uc interface circuit .................................................. 26 figure 19: general input circuit ............................................................................................................. 27 figure 20: off_req interface circuit ................................................................................................... 27 figure 21: 32 - pin qfn package dimensions ......................................................................................... 28 tables table 1: 73S8009CN pin definitions ........................................................................................................ 5 table 2: absolute maximum device ratings ............................................................................................ 9 table 3: recommended operating cond itions ......................................................................................... 9 table 4: dc smart card interface requirements ................................................................................... 10 table 5: digital signals characteristics .................................................................................................. 12 table 6: dc characteristics ................................................................................................................... 13 table 7: voltage / temperature fault detection circuits ......................................................................... 13 table 8: thermal characteristics ........................................................................................................... 13 table 9: order numbers and packaging marks ...................................................................................... 29
ds_8009cn_026 73S8009CN data sheet rev. 1.4 5 1 pinout the 73S8009CN is supplied as a 32 - pin qfn package. 6 7 8 9 5 4 3 2 1 17 18 19 20 24 23 22 21 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 lin vpc rdy pres i/o on/off dm gnd vdd rstin off_ack aux2 aux1 gnd clk rst vcc vp teridian 73S8009CN test1 clkin dp aux2uc aux1uc i/ouc cs sc/usb cmdvcc5 cmdvcc3 off_req test2 gnd off figure 2 : 73S8009CN 32 - pin qfn pinout table 1 describes the pin functions for the device. table 1 : 73S8009CN pin definitions pin name pin number type equi valent circuit description card interface i/o 22 io figure 17 card i/o: data signal to/from smart card. includes an 11k pull - up resistor to v cc will be tri - stated when sc/ usb is set low. aux1 21 io f igure 17 aux1: auxiliary data signal to/from smart card for synchronous smart card operation. smart card usb dp signal for is0 - 7816 - 12 usb smart card operation. includes an 11k pull - up resistor to v cc for synchronous / asynchronous operation only. au x2 20 io figure 17 aux2: auxiliary data signal to/from smart card for synchronous smart card operation. smart card usb dm signal for is0 - 7816 - 12 usb smart card operation. includes an 11k pull - up resistor to v cc for synchronou s / asynchronous operation only. rst 18 o figure 16 card reset: provides reset (rst) signal to card. rst is the pass through signal on rstin. internal control logic will hold rst low when card is not activated or vcc is too low . will be tri - stated when sc/ usb is set low.
73S8009CN data sheet ds_8009cn_026 6 rev. 1.4 pin name pin number type equi valent circuit description clk 16 o figure 15 card clock: provides clock signal (clk) to card. clk is the pass through of the signal on pin clkin. internal control logic will hold clk low when card is not act ivated or vcc is too low. will be tri - stated when sc/ usb is set low. pres 14 i figure 19 smart card presence switch: active high indicates card is present. smart card activation will not be permitted unless pres is active. vcc 19 pso figure 13 card power supply ? logically controlled by sequencer, output of ldo regulator. requires an external 0.47uf low esr filter capacitor to gnd. gnd 17 gnd ? card ground. host processor interface cs 12 i figure 19 chip select. when cs = 1, the control and signal pins are configured normally. when cs is set low, cmdvcc% , rstin, and cmdvcc# are latched. i/ouc, aux1uc, and aux2uc are set to high - impedance pull - up mode and do not pass data to or from the smart card. signals rdy and off are disabled to prevent a low output and the internal pull - up resistors are disconnected. should be tied to vdd when a single 73S8009CN is used. off 32 o figure 12 interrupt sign al to the processor. active low - multi - function indicating fault conditions and card presence. open drain output configuration ? it includes an internal 20k pull - up to v dd. pull - up is disabled in power down state and cs = 0 modes. i/ouc 1 io figure 18 system controller data i/o to/from the card. includes an 11k pull - up resistor to v dd. aux1uc 2 io figure 18 system controller auxiliary data i/o to/from the card for synchronous / asynchronous oper ation mode. connection to aux1 is opened when sc/ usb is low. includes an 11k pull - up resistor to v dd. aux2uc 3 io figure 18 system controller auxiliary data i/o to/from the card for synchronous / asynchronous operation mode. connection to aux2 is opened when sc/ usb is low. includes an 11k pull - up resistor to v dd. sc/ usb 13 i figure 19 smart card interface enable, usb interface disable. pin is provided with a weak pull - up. when high, the 73S8009CN operates in synchronous / asynchronous operation mode. when low, clk, rst i/o, aux1, and aux2 are tri - stated. pin aux1 is connected to pin dp and pin aux2 is connected to pin dm. dp 25 io figure 14 usb d+ connection to / from u sb controller. when sc/ usb is set low, this pin is electrically connected to the aux1 pin, otherwise it is isolated.
ds_8009cn_026 73S8009CN data sheet rev. 1.4 7 pin name pin number type equi valent circuit description dm 23 io figure 14 usb d - connection to / from usb controller. when sc/ usb is set low, this pin is electrica lly connected to the aux1 pin, otherwise it is isolated. cmdvcc% cmdvcc# 4 5 i i figure 19 logic low on one or both of these pins will cause the ldo regulator to ramp the vcc supply to the smart card and smart card interface to t he value described in the following table: cmdvcc% cmdvcc# vcc output voltage 0 0 1.8v 0 1 5.0v 1 0 3.0v 1 1 vcc off note: see card power supply and voltage supervision for more details. rstin 6 i figure 19 reset input: t his signal is the reset command to the card. rdy 8 o figure 12 signal to controller indicating the 73S8009CN is ready because v cc is above the required value after cmdvcc% and/or cmdvcc# is asserted low. a 20k pull - up resistor to v dd is provided internally. pull - up is disabled in power down state and cs=0 modes. on/off 24 i figure 11 power control pin. connected to normally open spst switch to ground. closing switch for durati on greater than de - bounce period will turn 73S8009CN circuit ?on?. if the 73S8009CN is ?on,? closing the switch will turn 73S8009CN to ?off? state after the de - bounce period and off_req/off_ack handshake. can be controlled by a host processor digital ou tput. off_req 11 o figure 19 digital output. request to the host system controller to turn the 73S8009CN off. if on_off switch is closed (to ground) for de - bounce duration and circuit is ?on,? off_req will go high (request to t urn off). connected to off_ack via 100k ? internal resistor. off_ack 13 i figure 19 setting off_ack high will power ?off? all analog functions and disconnect the 73S8009CN from v pc . the pin has an internal 100k resistor connect ion to off_req so that when not connected or no host interaction is required, the acknowledge will be true and the circuit will turn ?off? after the deactivation sequence is completed. miscellaneous clkin 7 i figure 19 clock sig nal source for the card clock. test1 10 ? ? factory test pin. this pin must be tied to gnd. test2 30 ? ? factory test pin. this pin must be tied to gnd.
73S8009CN data sheet ds_8009cn_026 8 rev. 1.4 pin name pin number type equi valent circuit description power supply and ground vdd 29 pso figure 13 system interface supply vo ltage output and supply voltage for companion controller circuit (40ma maximum source capability). requires a minimum of two 0.1 f capacitors to ground for proper decoupling. vpc 26 psi figure 13 power supply source for main vo ltage converter circuit. a 10 f and a 0.1 f ceramic capacitor must be connected to this pin. lin 27 psi figure 13 connection to 10 h inductor for internal step up converter. note: inductor must be rated for 400ma maximum peak c urrent. vp 15 pso figure 13 intermediate output of main converter circuit. requires an external 4.7 f low esr filter capacitor to gnd. gnd 28, 31 gnd ? ground.
ds_8009cn_026 73S8009CN data sheet rev. 1.4 9 2 electrical specifications this section provides the following: ? absolute maximum ratings ? recommended operating conditions ? smart card interface requirements ? digital signals characteristics ? voltage / temperature fault detection circuits ? thermal characteristics 2.1 absolute maximum ratings table 2 lists the maximum operating conditions for the 73S8009CN . permanent device damage may occur if absolute maximum ratings are exceeded. exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. table 2 : absolute maximum device ratings parameter rating supply voltage v pc - 0.5 to 7.0 vdc v dd - 0.5 to 4.0 vdc input voltage for digital inputs - 0.3 to (v dd +0.5) vdc storage temperature - 65 to 150c pin voltage (except card interface) - 0.3 to (v dd + 0.5) vdc pin voltage (card interface) - 0.3 to (v cc + 0.3) vdc pin voltage, lin pin 0.3 to 6.5 vdc esd tolerance ? card interface, dp and dm pins +/ - 6kv esd tolerance ? other pins +/ - 2kv pin current, except lin 200 ma pin current, lin + 500 ma in, - 200 ma out 2.2 recommended operating conditions function operation should be restricted to the recommended operating conditions specified in table 3 . table 3 : recommended operating conditions parameter rating supply voltage v pc 2.7 to 6.5 vdc ambient operating temperature - 40c to +85c
73S8009CN data sheet ds_8009cn_026 10 rev. 1.4 2.3 smart card interface requirements table 4 lists the 73S8009CN smart card interface requirements. table 4 : dc smart card interface requirements symbol parameter condition min nom max unit card power supply (v cc ) regulator general conditions: - 40c < 85c, 2.7 v < v pc < 6.5 v v cc card supply voltage including ripple and noise in active mode - 0.1 ? 0.1 v inactive mode i cc = 1ma - 0.1 ? 0.4 v active mode; i cc <65ma; 5v 4.65 ? 5.25 v active mode; i cc < 65ma; 3v 2.85 ? 3.15 v active mode; i cc < 40ma; 1.8v 1.68 ? 1.92 v active mode; single pulse of 100ma for 2 s; 5 volt, fixed load = 25ma 4.6 ? 5.25 v active mode; single pulse of 100ma for 2 s; 3v, fixed load = 25ma 2.76 ? 3.15 v active mode; current pulses of 40nas with peak |i cc | <200ma, t <400ns; 5v 4.6 ? 5.25 v active mode; current pulses of 40nas with peak | i cc | <200ma, t <400ns; 3v 2.7 ? 3.15 v active mode; current pulses of 20nas with peak |i cc | <100ma, t <400ns; 1.8v 1.62 ? 1.92 v v ccrip v cc ripple f ripple = 20khz ? 200mhz ? 350 mv i ccmax card supply output current static load current, v cc >1.65 ? 40 ma static load current, v cc >4.6 or 2.7 volts as selected ? 65 ma i ccf i cc fault current class a, b (5v and 3v) 75 ? 150 ma class c (1.8v) 55 ? 130 ma v s vcc slew rate, rise and fall c = 0.5 f 0.10 0.30 0.70 v/s v rdy vcc ready voltage (rdy = 1) 5v operation, vcc rising 4.6 ? ? v 3v operation, vcc rising 2.75 ? ? v 1.8v operation, vcc rising 1.65 ? ? v v ccf rdy = 0 (v cc voltage supervisor threshold) v cc = 5v ? ? 4.6 v c vpc external filter cap for v pc 8.0 10.0 12.0 f cvp external filter cap for vp 2.0 4.7 6.8 f c f external filter capacitor (v cc to gnd) c f should be ceramic with low esr (<100m ? ). 0.2 0.47 1.0 f c vdd vdd filter capacitor 0.2 ? 1.0 f
ds_8009cn_026 73S8009CN data sheet rev. 1.4 11 symbol parameter condition min nom max unit interface requirements ? data signals: i/o, aux1, aux2, and host interfaces: i/ouc, aux1uc, aux2uc, dp, dm. i shortl , i shorth , and v inact requirements do not pertain to i/ouc, aux1uc, aux2uc v oh output level, high (i/o, aux1, aux2) i oh =0 0.9 * v cc ? v cc +0.1 v v oh output level, high (i/ouc, aux1uc, aux2uc) i oh = - 40 a 0.75 v cc ? v cc +0.1 v i oh =0 0.9 v dd ? v dd +0.1 v v ol output level, low (i/o, aux1, aux2) i oh = - 40 a 0.75 v dd ? v dd +0.1 v i ol =1ma ? ? 0.15 *v cc v v ol output level, low (i/ouc, aux1uc, aux2uc) i ol =1ma ? ? 0.3 v v ih input level, high (i/o, aux1, aux2) 0.6 * v cc ? v cc +0.30 v v ih input level, high (i/ouc, aux1uc, aux2uc) 0.6 * v dd ? v dd +0.30 v v il input level, low (i/o, aux1, aux2) - 0.15 ? 0.2 * v cc v v il input level, low (i/ ouc, aux1uc, aux2uc) - 0.15 ? 0.2 * v dd v v in act output voltage when outside of session i ol = 0 ? ? 0.1 v i ol = 1ma ? ? 0.3 v i leak input leakage v ih = v cc ? ? 10 a ifloat input current input current with sc/ usb = 0 - 2 ? +2 a i il input current, l ow (i/o, aux1, aux2) v il = 0 ? ? 0.65 ma i il input current, low (i/ouc, aux1uc, aux2uc) v il = 0 ? ? 0.7 ma i shortl short circuit output current for output low, shorted to v cc through 33 ? ? ? 15 ma i shorth short circuit output current for output high, shorted to ground through 33 ? ? ? 15 ma t r , t f output rise time, fall times for i/o, aux1, aux2, c l = 80pf, 10% to 90%. for i/ouc, aux1uc, aux2uc, cl=50pf, 10% to 90%. ? ? 100 ns t ir , t i f input rise, fall times ? ? 1 s r pu internal pull - up resistor output stable for >200ns 8 11 14 k ? fd max maximum data rate ? ? 1 mhz t fd io delay, i/o to i/ouc, aux1 to aux1uc, aux2 to aux2uc,i/ouc to i/o, aux1uc to aux1, aux2uc to aux2 (respectively falling edge to falling edge and rising edge to rising edge) edge from master to slave, measured at 50% 60 100 200 ns t rd io ? 15 ? ns c in input capacitance ? ? 10 pf inusboff input current usb off 0 < vdm, vdp <3.3v, vcc=5v, sc/ usb =1 - 2 ? +2 a rs witch resistance d to aux 0 < vdm, vdp < 3.3v, vcc=5v, sc/ usb =0 0.5 2 6 ?
73S8009CN data sheet ds_8009cn_026 12 rev. 1.4 symbol parameter condition min nom max unit reset and clock for card interface, rst, clk v oh output level, high i oh = - 200 a 0.9 * v cc ? v cc v v ol output level, low i ol =200 a 0 ? 0.15 *v cc v v in act output voltage when outside of session i ol = 0 ? ? 0.1 v ifloat input current i ol = 1ma ? ? 0.3 v input current with sc/ usb = 0, open circuited - 5 ? +5 a i rst_lim output current limit, rst ? ? 30 ma i clk_lim output current li mit, clk ? ? 70 ma t r , t f output rise time, fall time c l = 35pf for clk, 10% to 90% ? ? 12 ns c l = 200pf for rst, 10% to 90% ? ? 100 ns duty cycle for clk c l =35pf, f clk 20mhz, clkin duty cycle is 48% to 52%. 45 ? 55 % 2.4 digital signals charact eristics table 5 lists the 73S8009CN digital signals characteristics. table 5 : digital signals characteristics symbol parameter condition min nom max unit digital i/o (except for i/ouc, aux1uc, aux2uc; se e smart card interface requirements for those specifications) v il input low voltage - 0.3 ? 0.8 v vil offack input low voltage for off_ack pin off_req pin = vdd - 0.3 ? 0.7 v v ih input high voltage 1.8 ? v dd + 0.3 v v ol output low voltage i ol = 2ma ? 0.45 v v oh output high voltage i oh = - 1ma v dd - 0.45 ? v r out pull - up resistor; off, rdy 14 20 26 k ? r ack resistor between off_req and 0ff_ack 70 100 130 k ? | i il1 | input leakage current gnd < v in < v dd ? ? 5 a t sl time fro m cs goes high to interface active 50 ? ? ns t dz time from cs goes low to interface inactive, hi - z 50 ? ? ns t is set - up time, control signals to cs rising edge 50 ? ? ns t si hold time, control signals from cs rising edge ? ? 50 ns t id set - up time, control signals to cs fall 50 ? ? ns t di hold time, control signals from cs fall ? ? 50 ns
ds_8009cn_026 73S8009CN data sheet rev. 1.4 13 2.5 dc characteristics table 6 lists the dc characteristics. table 6 : dc characteristics symbol parameter conditio n min nom max unit v dd v dd voltage 2.7v < vpc < 6.5v, i vddext < 40ma. 3.0 3.3 3.6 v i ddext v dd current to external load ? ? 40 ma i vpc supply current vpc = 2.7v, v cc off, i dd = 0 ? 1.7 ? ma vpc = 3.3v, v cc off, i dd = 0 ? 1.1 ? ma vpc = 5.0v, v cc off, i dd = 0 ? 0.7 ? ma off mode ? 0.01 1 a 2.6 voltage / temperature fault detection circuits table 7 lists the voltage /temperature fault detection circuits. table 7 : voltage / temperature fault det ection circuits symbol parameter condition min nom max unit i dd max vdd over - current limit 40 ? 100 ma i ccf card overcurrent fault 80 ? 150 ma i ccf1p8 card overcurrent fault v cc = 1.8v 60 ? 130 ma 2.7 thermal characteristics tabl e 8 lists the thermal characteristics. table 8 : thermal characteristics symbol parameter condition min nom max unit tj junction temperature ? ? 125 c ja thermal resistance, junction - to - ambient ? 70 ? c/w jc thermal resistance, junction - to - case ? 6 ? c/w 3 applications information this section provides general usage information for the design and implementation of the 73S8009CN. the docume nts listed in related documentation provide more detailed information. 3.1 example 73S8009CN schematics figure 3 shows a typical application schematic for the implementation of the 73S8009CN with a main syst em switch . figure 4 shows a typical application schematic for the implementation of the 73S8009CN without a main system switch . note that minor changes may occur to the reference material from time to time and th e reader is encouraged to contact teridian for the latest information.
73S8009CN data sheet ds_8009_026 14 rev. 1.4 clkin_from_uc c8 0.47 f, off_ack_from_uc off _interrupt_to_uc clk track should be routed far from rst, i/o, c4 and c8 notes: 1) vpc = 2.7v to 6.5v dc i/ouc_to/from_uc card detection switch is normally closed vdd aux1uc_to/from_uc aux2uc_to/from_uc rstin_from_uc low esr (<100mohms) should be placed near the sc connecter contact cmdvcc% _from_uc r2 20k smart card connector 1 2 3 4 5 6 7 8 9 10 vcc rst clk c4 gnd vpp i/o c8 sw-1 sw-2 cmdvcc# _from_uc rdy_status _to_uc c4 see note 1 off_req _to_uc 0 c7 4.7 f c6 27pf c5 27pf see note 2 2) resistor footprint is included in case some filtering is needed on clk vpc 12 10 11 13 15 16 14 32 qfn 73s80009cn 1 2 3 4 5 6 7 8 cs test1 gnd vpc clkin aux2 rdy sc /usb pres i/o aux1 dm clk rst vcc test2 cmdvcc% rstin vdd gnd off aux2uc aux1uc i/ouc cmdvcc# vp off_ack off_req on/off dp lin gnd 17 18 19 20 21 23 24 22 9 28 27 25 26 32 31 29 30 10 f 10 h vdd pushbutton switch sw1 vdd _supply _to_uc see note 3 see note 3 3) capacitors c4 and c5 are provisional and their footprints should be added for added noise rejection if necessary. 4) inductor must be rated for 400 ma maximum peak current. see note 4 5) v dd - 3.3v, +/- 0.3v, 40ma max. schematic assumes vdd supplies power to the host controller. requires min two 0.1 f caps to gnd) see note 5 c2 0.1 f c1 0.1 f usb d+ to/from_uc usb d- to/from_uc sc /usb _from_uc 6) the rdy signal is optional. a short delay before releasing rstin should suffice for the rdy signal function. c3 0.1 f see note 6 figure 3 : typical 73S8009CN application schematic with a main system switch
ds_8009cn_026 73S8009CN data sheet rev. 1.4 15 clkin_from_uc c7 0.47 f, off _interrupt_to_uc clk track should be routed far from rst, i/o, c4 and c8 notes: 1) vpc = 2.7v to 6.5v dc i/ouc_to/from_uc card detection switch is normally closed vdd aux1uc_to/from_uc aux2uc_to/from_uc rstin_from_uc low esr (<100mohms) should be placed near the sc connecter contact cmdvcc% _from_uc r2 20k smart card connector 1 2 3 4 5 6 7 8 9 10 vcc rst clk c4 gnd vpp i/o c8 sw-1 sw-2 cmdvcc# _from_uc rdy_status _to_uc c3 see note 1 0 c2 4.7 f c6 27pf c5 27pf see note 2 2) resistor footprint is included in case some filtering is needed on clk vpc 12 10 11 13 15 16 14 32 qfn 73s80009cn 1 2 3 4 5 6 7 8 cs test1 gnd vpc clkin aux2 rdy sc /usb pres i/o aux1 dm clk rst vcc test2 cmdvcc% rstin vdd gnd off aux2uc aux1uc i/ouc cmdvcc# vp off_ack off_req on/off dp lin gnd 17 18 19 20 21 23 24 22 9 28 27 25 26 32 31 29 30 10 f 10 h vdd vdd _monitor _to_uc see note 3 see note 3 3) capacitors c5 and c6 are provisional and their footprints should be added for added noise rejection if necessary. 4) inductor must be rated for 400 ma maximum peak current. see note 4 5) v dd - 3.3v, +/- 0.3v, 40ma max. schematic assumes vdd is monitored by the host controller. requires min two 0.1 f caps to gnd) see note 5 c2 0.1 f c1 0.1 f usb d+ to/from_uc usb d- to/from_uc sc /usb _from_uc on/off_control_from_uc 0 10k 47k 47k 47k 6) resistors are necessary to provide isolation between powered host and "off" 73S8009CN. signals should be driven low in this condition. see note 6 7) the rdy signal is optional. a short delay before releasing rstin should suffice for the rdy signal function. see note 7 c4 0.1 f figure 4 : typical 73S8009CN application schematic without a main system switch
73S8009CN data sheet ds_8009cn_001 16 rev. 1.4 3.2 power supply and converter the 73S8009CN power supply and converter circuitry takes power from the v pc input pin. the power supplied to v pc pin is converted to the volta ge v p utilizing an inductive, step - up converter. a series power inductor (nominal value = 10 h) is connected from pin vpc to pin lin, and a 10 f and a 0.1 f filter capacitor must be connected to v pc . note: when the v pc input voltage exceeds the nominal v p voltage (approximately 5.5v), the switching operation of the converter stops and the converter acts as a pass through for v pc to v p . switching operation will automatically resume when v pc falls below the nominal v p voltage. v p requires a 4.7 f filter c apacitor and will have a nominal value of 5.5 volts during normal operation. v p is used by the smart card interface circuits (clk, rst, i/o, aux1, and aux2) and is the source of the regulated smart card supply v cc . v cc can be selected for values of 5v, 3 v, and 1.8v. the power supply output v dd is also produced from v p . v dd is used by the 73S8009CN circuit for logic, input / output buffering with the host. in addition, v dd can be used as a 3.3v regulated power supply for some external circuitry provided that no more than 40ma is needed (simultaneously to the 65ma current drawn from v cc ). 3.3 interface function - on/off modes a power on/off function is provided such that the circuit will be inoperative during the ?off? state, consuming minimum current from v pc . option 1: 73S8009CN supplies host/system power controlled by push button on/off switch: refer to figure 3 for a typical electrical schematic when using an on/off system switch. the on/off pin shall be connected to an spst sw itch to ground. if the circuit is off and the switch is closed for a de - bounce period of approximately 100ms, the circuit shall go into the ?on? state wherein all functions are operating in normal fashion. if the circuit is in the ?on? state and the on/o ff pin is connected to ground for a period greater than the de - bounce period, off_req will be asserted high and held regardless of the state of on/off. typically, the off_req signal is presented to a host controller that will assert off_ack high when it h as completed all shutdown activities. when off_ack is set high, the circuit will de - activate the smart card interface if required and turn off all analog functions and the v dd supply for the logic and companion circuits. the off_ack pin is connected inte rnally to off_req with a resistor such that if off_ack is unconnected, the action of off_req will assert off_ack high. in this configuration, the circuit shall go into the ?off? state immediately if the interface is deactivated or immediately after deacti vation if previously activated.. the default state upon application of power to v pc is the ?off?. note that at any time, the controller may assert off_ack and the 73S8009CN will go into the ?off? state (regardless of activity on the on/off main system sw itch). option 2: on/off status driven from the host processor (no system switch): refer to figure 4 for a typical electrical schematic when controlling the on/off pin via host control. the on/off pin can be connected to a host digital control signal to turn the 73S8009CN on or off. the host should monitor the v dd supply to determine when the switch debounce time has been achieved so the 73S8009CN can switch states (on or off). when the 73S8009CN is off, the host should drive t he on/off pin low to initiate the turn on process. the signal must remain low until the v dd supply voltage goes to 3.3v. the 73S8009CN is now on and the on/off pin should be driven back high. to turn off the 73S8009CN, the host should drive the on/off s ignal low until the v dd supply goes to 0v. the 73S8009CN is now off and the on/off pins should be driven back high. see note 6 .
ds_8009cn_026 73S8009CN data sheet rev. 1.4 17 important notes: 1. when the host is not powered by the v dd supply of the 73S8009CN, special care mu st be taken as the host signals going to the 73S8009CN can be active when the device is powered off. this can create issues such as excessive current drain on the control signals and potentially prohibit proper turn on of the 73S8009CN. series resistors on the input signals (except the on/off input) are recommended to provide isolation and prevent any potential problems. the recommended value of these resistors is 47k . it is also necessary for the host to set these input signals to the low state (excep t for on/off) when the 73S8009CN is off. false activation of the card is possible if the cmdvcc# or cmdvcc% inputs are low (with a card inserted) when the 73S8009CN is powered on. for this reason, the proper sequencing of the 73S8009CN is required. the cmdvcc# or cmdvcc% inputs must be set high immediately before the on/off input is taken low to turn on the 73S8009CN. the time between setting the cmdvcc# or cmdvcc% inputs high and the setting of the on/off input set low should be kept to a minimum as th e cmdvcc# or cmdvcc% inputs, when set high with the 73S8009CN off, will draw significant current under these conditions. the 47k series resistors will mitigate this current draw. however, some additional current will be drawn through the resistors to th e cmdvcc# or cmdvcc% inputs during this time so it should be kept to a minimum. 2. for applications where on/off is controlled by the host, the off_req and off_ack signals do not need to be connected to the host. when the off_ack pin is left unconnected, the 73S8009CN will turn off properly by the action of the internal resistor connection to off_req. 3. if the host is capable of selectively monitoring the i/o line, it can be used in place of the v dd supply monitor as it is tied to the v dd supply through a pull up resistor when the smart card interface is not activated. 4. when the 73S8009CN is powered off, the host will not be able to detect a card event (card insertion/removal). if this function is necessary, then the host must monitor the card connector switch s eparately. 5. for systems that do not use vdd to power the host controller, the host interface signals must operate at 3.3v as the 73S8009CN digital logic operates off the v dd (3.3v) supply regardless of the value of the v pc supply. 6. the on/off pin is internal ly pulled up to v pc through a 24k resistor. special care must be taken if the host signal controlling the on/off signal is running at a voltage different from v pc . if this is the case, then either the host control signal must be a maximum v pc supply tol erant open drain output or an external circuit should provide some isolation between the host control signal and the on/off pin. 7. for those systems that require low power operation or are battery operated, the host controller circuit firmware should place t he 73S8009CN in the off state if no card activity is required.
73S8009CN data sheet ds_8009cn_026 18 rev. 1.4 3.4 system controller interface five separate digital inputs and two outputs allow direct control of the card interface from the host: ? pin cs: chip select control. ? pin cmdvcc# and/or cmdvcc% : wh en low, starts an activation sequence. ? pin rstin: controls the card rst signal. ? pin sc/ usb : routes auxx signals to auxxuc or usb dx pins and provides proper tri - stating functionality. ? pin rdy: indicates when smart card power supply is stable and ready. ? pin off : indicator of card presence and any card fault conditions. interrupt output to the host: when the card is not activated, the off pin informs the host about the card presence only (low = no card in the reader, high = card inserted). when cmdvcc ( #/% signals) is/are set low (card activation sequence requested from the host), low level on off means a fault has been detected (e.g. card removal during card session, or voltage fault, or thermal / over - current fault) that automatically initiates a deactivat ion sequence. the smart card pass through signals are enabled when the rdy conditions are met. 3.5 card power supply and voltage supervision the 73S8009CN smart card interface ic incorporates an ldo voltage regulator for the card power supply, v cc (v p to v cc conversion uses an internal ldo). the voltage output is controlled by the digital input sequence of cmdvcc# and cmdvcc% . this regulator is able to provide either 1.8v, 3v or 5v card voltage sourced from the v p power supply. internal digital circuitry i s also powered by the v p power supply (except for the on/off circuitry which is powered from v pc ). a voltage supervisor checks the value of the voltage v cc . a card deactivation sequence is forced upon fault detected by voltage supervisor, overcurrent con dition, or card removal event. the voltage regulator can provide a card current of 65ma in compliance with emv 4.1 for 3 - v and 5 - v cards. the signals cmdvcc# and cmdvcc% control the turn - on, output voltage value, and turn - off of v cc . when either signal is asserted low, v cc will ramp to the selected value or if both signals are asserted low (within 400ns of each other), v cc will ramp to 1.8v. these signals are edge triggered. if cmdvcc% is asserted low (to command v cc to be 5v) and at a much later time (greater than 2 s, typically), cmdvcc# is asserted low, it will be ignored (and vice versa.) at the assertion (low) of either or both cmdvcc ( #/% signals), v cc will rise to the requested value. when v cc rises to an acceptable value, and stays above that value for approximately 20 s, rdy will be set high. approximately 510 s after the fall of cmdvcc ( #/% ), the circuit will check the see if v cc is at or above the required minimum value (indicated by rdy=1) and if not, will begin an emergency deactivation s equence. during the 510 s time, card removal, or de - assertion of cmdvcc ( #/% ) shall also initiate an emergency deactivation sequence. the circuit provides over - current protection and limits icc to 150ma, maximum for self - protection. when an over - current condition is sensed, the circuit will invoke a de - activation sequence.
ds_8009cn_026 73S8009CN data sheet rev. 1.4 19 3.6 activation and de - activation sequence the host controller is fully responsible for the activation sequencing of the smart card signals clk, rst, i/o, aux1 and aux2. all these signa ls are held low by the 73S8009CN when the card is in the de - activated state. upon card activation (the fall of cmdvcc ( #/% )), all the signals are held low by the 73S8009CN until rdy goes high. the host should set the signals rstin, i/ouc, clkin, aux1uc a nd aux2uc low prior to activating the card and allow rdy to go high before transitioning any of these signals. in order to initiate activation, the card must be present and off must be high. cmdvcc5 or cmdvcc3 vcc i/ouc i/o rdy rstin rst clkin clk ignored ignored ignored i/o, aux1, aux2, clk, rst are held low until rdy = 1 and cmdvccx = 0 i/o = i/ouc if rdy=1 clk=clkin if rdy=1 rst = rstin if rdy=1 t1 at t1 (500us), if rdy=0 or overcurrent, circuit will de-activate (safety feature) vcc valid figure 5 : activation sequence deactivation is initiated either by the system controller by setting both cmdvcc ( #/% ) high, or automatically in the event of hardware faults or assertion of the off_ack signal. hardware faults are over - current, under - voltage, and c ard extraction during the session. the host can manage the i/o signals, clkin, rstin, and cmdvcc ( #/% ) to create other de - activation sequences for non - emergency situations. the following steps show the deactivation sequence and the timing of the card con trol signals when the system controller sets the cmdvcc(x)b high: 1. rst goes low at the end of time t1. 2. de - assert clk at the end of time t2. 3. i/o goes low at the end of time t3. exit reception mode. 4. de - assert internal vcc_on at the end of time t4. after a delay, vcc is de - asserted. note: since the 73S8009CN does not control the waveshape of clk (it is determined by the input form the host clkin), there is no guarantee that the duty cycle of the last clk high pulse will conform to duty cycle requirements du ring an emergency deactivation.
73S8009CN data sheet ds_8009cn_026 20 rev. 1.4 cmdvcc rst clk i/o vcc_on vcc t1 t2 t3 t4 t5 figure 6 : deactivation sequence 3.7 off and fault detection there are two different cases that the system controller can monitor the off signal: to query regarding the ca rd presence outside card sessions, or for fault detection during card sessions. outside a card session: in this condition, cmdvcc ( #/% ) are always high, off is low if the card is not present, and high if the card is present. because it is outside a card session, no fault detection can occur and it will not act upon the off signal. no deactivation is required during this time. during a card session: cmdvcc# and/or cmdvcc% is always low, and off falls low if the card is extracted or if any fault detection is detected. at the same time that off is set low, the sequencer starts the deactivation process and the host should stop all transitions on the signal lines. figure 4 shows the timing diagram for the signals cmdvcc ( #/% ) , pres, and off during a card se ssion and outside the card session. pres off cmdvcc vcc outside card session within card session off is low by card extracted off is low by any fault within card session figure 7 : off activity
ds_8009cn_026 73S8009CN data sheet rev. 1.4 21 3.8 chip selection the cs pin allows multiple circuits to operate in parallel, driven from the same host control bus. when cs is high, the pins rstin, cmdvcc% , cmdvcc# and clkin control the chip as described. the pins i/ouc, aux1uc, and aux2uc have 11k ? pull - up resistors and operate to transfer data to the smart card via i/o, aux1, and aux2 when the smart card is activated. the signals off and rdy have 20k ? pull - up resistors. when cs goes low, the states of the pins rstin, cmdvcc% , cmdvcc , and clkin are latched and held internally. the pull - up for pins i/ouc, aux1uc, and aux2uc become a very weak pull - up of approximately 3 microamperes. no tr ansfer of data is possible between i/ouc, aux1uc, aux2uc and the smart - card signals i/o, aux1, and aux2. the signals off and rdy are set to high impedance and the internal pull - up resistors of 20k ? are disconnected. with regard to de - activation, cs does not affect the operation of the fault sensing circuits and card sense input. cs does not affect the action of sc/ usb . cs off, i/ouc, aux1uc, aux2uc control signals functional hi-z state hi-z state t sl t dz t is t si t id t di figure 8 : cs timing definitions
73S8009CN data sheet ds_8009cn_026 22 rev. 1.4 3.9 i/o circuitry and timing the states of the i/o , aux1, and aux2 pins are low after power on reset and they are in high when the activation sequencer turns on the i/o reception state. see the activation and de - activation sequence section for more details on when the i/o reception is enabled. the states of i/ouc, aux1uc, and aux2uc are high after power on reset. within a card session and when the i/o reception state is turned on, the first i/o line on which a falling edge is dete cted becomes the input i/o line and the other becomes the output i/o line. when the input i/o line rising edge is detected, then both i/o lines return to their neutral state. figure 6 shows the state diagram of how the i/o and i/ouc lines are managed to become input or output. neutral state i/ouc in i/o reception i/oicc in no yes no no no yes no yes i/o & not i/ouc i/ouc & not i/o i/ouc i/o yes yes figure 9 : i/o and i/ouc state diagram
ds_8009cn_026 73S8009CN data sheet rev. 1.4 23 the delay between the i/o signals is shown in figure 10 . i/o i/ouc t i/o_hl t i/o_lh t i/ouc_hl t i/ouc_lh delay from i/o to i/ouc: t i/o_hl = 100ns t i/o_lh = 15ns delay from i/ouc to i/o: t i/ouc_hl = 100ns t i/ouc_lh = 15ns figure 10 : i/o ? i/ouc delays - timing diagram
73S8009CN data sheet ds_8009cn_026 24 rev. 1.4 4 equivalent circuits this section provides illustrations of circuits equivalent to those described in the pinout section. pin esd vpc 24k figure 11 : on_off pin pin vdd strong nfet data from circuit output disable 20k esd figure 12 : open drain type ? off and rdy pin esd to internal circuits figure 13 : power input/output circuit, vdd, lin, vpc, vcc, vp
ds_8009cn_026 73S8009CN data sheet rev. 1.4 25 pin esd to aux1 or aux2 pad 2 ohms figure 14 : usb ? dm, dp pins clk pin vcc very strong pfet very strong nfet from circuit esd esd figure 15 : smart card clk driver circuit rst pin vcc strong pfet strong nfet from circuit esd esd figure 16 : smart card rst driver circuit
73S8009CN data sheet ds_8009cn_026 26 rev. 1.4 400ns delay io pin vcc strong pfet strong nfet rl=11k from circuit cmos to circuit esd esd figure 17 : smart card io, aux1, and aux2 interface circuit 400ns delay uc pin vdd strong pfet strong nfet rl=11k from circuit cmos to circuit esd esd figure 18 : smart card iouc, aux1uc and aux2uc interface circuit
ds_8009cn_026 73S8009CN data sheet rev. 1.4 27 pin vdd ttl to circuit pull-up disable very weak pfet esd very weak nfet pull-down enable esd note: pins cmdvcc% , cmdvcc# , cs, sc/ usb have the pull - up enabled. pins rstin, clkin, pres, ext_rst have the pull - down enabled. pin off_ack has a 100k resistor connected to pin off_req internally. figure 19 : general input circuit pin vdd strong pfet strong nfet data from circuit to off_ack pad output disable esd esd 100k ohm notes: strong pfet or nfet is approximately 100 very strong pfet or nfet is approximately 50 medium strength pfet is approximately 1k very weak pfet or nfet is approximately 1m the diodes represent esd protection devices that will conduct current if forward biased. figure 20 : off_req interface circuit
73S8009CN data sheet ds_8009cn_026 28 rev. 1.4 5 mechanical drawing 2.5 5 2.5 5 top view 1 2 3 0.2 min. 0.35 / 0.45 1.5 / 1.875 3.0 / 3.75 0.18 / 0.3 bottom view 1 2 3 0.25 0.5 0.5 0.25 3.0 / 3.75 1.5 / 1.875 0.35 / 0.45 chamfered 0.30 figure 21 : 32 - pin qfn package dimensions 0.85 nom. / 0.9max. 0.00 / 0.005 0.20 ref. seating plane side view
ds_8009cn_026 73S8009CN data sheet rev. 1.4 29 6 ordering information table 9 lists the order numbers and packaging marks used to identify 73S8009CN products. table 9 : order numbers and packaging marks part description order number packaging mark 73S8009CN - 32qfn 32- pin lead - free qfn 73S8009CN - 32im/f s8009cn 73S8009CN - 32qfn 32- pin lead - free qfn tape / reel 73S8009CN - 32imr/f s8009cn 7 related documentation the following 73S8009CN document is available from teridian semiconductor corporation: 73S8009CN 32qfn demo board user?s guide 8 contact information for more information about teridian semiconductor products or to check the availability of the 73S8009CN , contact us at: 6440 oak canyon road suite 100 irvine, ca 92618 - 5201 telephone: (714) 508 - 8800 fax: (714) 508 - 8878 email: scr.support@teridian.com for a complete list of worldwide sales offices, go to http://www.teridian.com .
73S8009CN data sheet ds_8009cn_026 30 rev. 1.4 revision history revision date description 1.0 10/23/2007 first publication. 1.1 11/6/2007 added the related documentation section and the contact information section. miscellan eous editorial changes. change the name of the ? sc_usb ? pin to ?sc/ usb ?. 1.2 1/21/2008 changed the dimension of the bottom view 32 - pin qfn package. 1.3 1/31/2008 added section 2.5, dc characteristics. 1.4 8/28 /2009 corrected the document number from ?ds _8009cn_001? to ?ds_8009 cn _026?. teridian semiconductor corporation is a registered trademark of teridian semiconductor corporation. simplifying system integration is a trademark of teridian semiconductor corporation. all othe r trademarks are the property of their respective owners. this data sheet is proprietary to teridian semiconductor corporation (tsc) and sets forth design goals for the described product. the data sheet is subject to change. tsc assumes no obligation re garding future manufacture, unless agreed to in writing. if and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infr ingement and limitation of liability. teridian semiconductor corporation (tsc) reserves the right to make changes in specifications at any time without notice. accordingly, the reader is cautioned to verify that a data sheet is current before placing ord ers. tsc assumes no liability for applications assistance. teridian semiconductor corp., 6440 oak canyon, suite 100, irvine, ca 92618 tel (714) 508 - 8800, fax (714) 508 - 8877, http://www.teridian.com

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